RMII Interface Overview
RMII interface has 12 signal lines, all signal names are described from the MAC layer side, the main # include four parts. One is the transmit data interface from the MAC layer to the physical layer, the second is the receive data interface from the MAC layer to the physical layer, the third is the clock interface between the physical layer and the MAC layer, and the fourth is the MDIO/MDC interface for data management between the MAC layer and the physical layer.
Interface image parsing
Pin Definition Analysis
TXD[1:0]: data send signal line, data bit width is 2, half of MII interface.
RXD[1:0]: data receiving signal lines, data bit width is 2, half of the MII interface.
TXEN (Transmit Enable): data transmit enable signal, same function as this signal line in MII interface.
RXER (Receive Error): data receiving error prompt signal, the same function as this signal line in the MII interface.
CLKREF: It is a 50MHz reference clock provided by an external clock source, which is different from the MII interface, in which the receive clock and transmit clock are separate, and both are provided by the PHY chip to the MAC chip. It should be noted that, because the data receiving clock is provided by an external crystal rather than extracted from the carrier signal, the data receiving part of the PHY layer chip needs to be designed with a FIFO to coordinate the two different clocks and provide a buffer when sending the received data, and the transmitting part of the PHY layer chip doesn’t need a FIFO to send the received data to the MAC directly. It sends the received data to the MAC directly.
CRSDV: This signal is a combination of the two signals RX_DV and CRS from the MII interface. When the medium is not idle, CRS_DV and RECLK are given in asynchronous fashion. When CRS ends earlier than RXDV (i.e., when the carrier disappears and there is still data in the queue to be transmitted), there is a toggle back and forth between 0 and 1 at the boundary of the half-bit group by CRSDV at a frequency of 25 MHz/2.5 MHz. As a result, the MAC is able to precisely recover the RXDV and CRS from the CRSDV.
At 100Mbps rate, TX/RX samples one data per clock cycle; at 10Mbps rate, TX/RX samples one data every 10 cycles, thus TX/RX data needs to be retained on the data line for 10 cycles, which is equivalent to sending a data 10 times.
When the PHY layer chip receives a valid carrier signal, the CRS_DV signal becomes valid, at this time, if there is no data in the FIFO, it will send out all 0 data to the MAC, and then when the FIFO is filled with valid data frames, the beginning of the data frames is the leading code of “101010-” crossover, when there are “01” bits in the data, it means the official data transmission starts, and the MAC chip detects this change and starts to receive data. When a valid data frame is filled in the FIFO, the beginning of the data frame is the leading code of “101010-” cross, when there is a “01” bit in the data, it represents the beginning of the official data transmission, and the MAC chip detects this change, so that it starts to receive the data.
When the external carrier signal disappears, CRSDV will become invalid, but if there is still data to be sent in the FIFO, CRSDV will become valid again in the next cycle, and then invalid and then valid again until the data in the FIFO is sent. If there is an invalid carrier signal or invalid data code during reception, RXER will become valid, indicating a physical layer chip reception error.
connection method
RMII connection for MAC-to-PHY
The RMII connection for MAC-to-PHY is relatively simple, just connect the appropriate signals directly.
