preamble
This article installs Gowin, Gowin’s development software, and describes the development environment and complete download and runtime of a program based on Gowin’s fpga.
Gowin Software
summarize
Gowin software is the FPGA development software of Guangdong Gowin Semiconductor Co.
download address
http://www.gowinsemi.com.cn
Apply for license
Apply for license at http://www.gowinsemi.com.cn/faq_view.aspx
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/572a5e03e78a44d582d5879ea74913a9.png)
There is also a harmonious way this process can be viewed:
http://www.corecourse.cn/forum.php?mod=viewthread&tid=29510
After downloading the software and getting the license it is time to install the software.
Installation of Gowin Software
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/8d59ed72c5e84444a43d37c89b122e93.png)
Then, there was no more then, it was straight up gone, it was the installation that was done.
License Registration
This is no license, open the installation directory:
boot software
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/ee35a42f04784855bf0bbeaf0966ef16.png)
Drag it out and place it on the Start screen:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/84477f1c76984abe82b258ca2885ae03.png)
Click to open:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/81306c35e68d42e0b1f628042ce35c00.png)
Above is the registration license failed or unregistered, go back and continue to register.
Configure the default path for Chinese and new projects
Fpga Development Process
Step 1: Open the software
Step 2: Create Project/Open Project
Step 3: Edit/add verilog source files
Add a verilog program source code here, take a random one from inside the demo (this is a demo program source code for inverted led light):
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/70d3122750264a76849215f4bdd3aae4.png)
Copy it to the project under src:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/66925902d95c4471ba6070a9057681d1.png)
Then add the next verilog file:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/ce9205729954422b9c1085f8b9583bac.png)
Above is the way to create a new file and below is the way to add an existing file:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/e3d547d066a74d3a902c2324d842023d.png)
Select the .v file in the src directory:
Step 4: RTL syntax analysis (equivalent to compilation for code programming)
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/4309edd42ebc446dbde239450ab10c8b.png)
Click on it:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/a33fbaa62e7b4e578cecf34b8041adbe.png)
Then the analysis and synthesis begins:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/7c40241b2a48457cbf36becf3eba3514.png)
Once completed, this is the generation of the fpga’s underlying resource circuit netlist:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/6f0b3b27ebc047fbb0aeab21572e893b.png)
When finished, Hierarchy displays the resources used by the module:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/9b6baea3ab6143a285af63a34cb0ac08.png)
Set the top-level file:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/0acfdd8926e14272ab90416f7494ecdb.png)
Which program does this one seem to run.
Step 5: Physical constraints
Go to the FloorPlanner interface and click I/O Constraints for I/O constraints, then assign pins and level standards according to your board.
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/b1810b8591c243fcbf84250efdcf8e9c.png)
A new box pops up:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/3e10002c3ec445eba6126b66ee661db2.png)
Click on I/O Constraints:
Step 6: Layout wiring
By clicking Process->Place&Route for layout and routing, if the layout and routing is successful, you will see “Bitstream generation completed”, which means that the fs file has been generated successfully, as follows:
Step 7: Board-level verification (equivalent to microcontroller in-circuit debugging)
The fs file is downloaded to the FPGA chip and is used to complete the configuration of the FPGA:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/ff5bf00796134bc2adf9ec39a0edfd39.png)
Device detected, confirming programming:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/c7557761a2a14b65bd780361d24b9456.png)
Online debugging results:
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/53987241d191495a9175c4eef352f896.png)
There are three lights on all the time, you can configure the lower pin output to be low (default pull-up high.):
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/d3f50a51bb714cd69a5eb9c33ffd11c5.png)
(Here it’s down and running.)
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/316730b5e8d84c92b7260f9c03762e80.png)
(Note: At this time is equivalent to the microcontroller to download the program to go down the online debugging, power failure is gone, need to download brush firmware)
Step 8: Program curing (equivalent to downloading the degree to the microcontroller)
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/95806bb8a5f9460fb8b7034664000038.png)
Then again, at a slower pace, the download completes:
fig. make a career out of it
Pitfall 1: download program stuck
concern
unresponsive and stuck
rationale
currently unknown
tackle
Continue to click run can open the second window, you can download, test found that the first inevitably stuck, stuck under the premise of opening the second, the second can be downloaded, if you turn off and then open is also a, or stuck, as a bug in this download software.
Pitfall 2: LED0 does not blink after download
concern
No blinking, all four lights on
rationale
Unconstrained Pin Output
tackle
To configure the pin constraints (actually configure the pin outputs)
![Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process Fpga development notes (II): Gowin FPGA development software Gowin and Gowin fpga basic development process](https://imgs.developpile.com/imgs/5de81e2d69a7488894bdb31fc3fc41d9.png)
Previous: The
Fpga development notes (I): high-cloud FPGA chip introduction, the start of the development board kit, the core board and base board introduction》
Next articleStay tuned…
Blog address for this post:
https://hpzwl.blog.csdn.net/article/details/135620590