Tag:fpga
-
Verilog Basic Syntax and Notes
basics 0.1 Modules A module in Verilog can be viewed as a black box with input and output ports, which has input and output interfaces (signals) to realize a function by putting inputs in the box to perform certain operations. (Similar to a function in C). Fig. 1 Schematic diagram of the module 0.1.1 Module […]